Regviz

Freescale Semiconductor /MKE16F16 /FTM2 /PWMLOAD

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PWMLOAD

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKE16F16/FTM1/PWMLOAD#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CH0SEL 0 (0)CH1SEL 0 (0)CH2SEL 0 (0)CH3SEL 0 (0)CH4SEL 0 (0)CH5SEL 0 (0)CH6SEL 0 (0)CH7SEL 0 (0)HCSEL 0 (0)LDOK 0 (0)GLEN 0 (0)GLDOK

HCSEL=0, CH1SEL=0, LDOK=0, CH0SEL=0, CH7SEL=0, GLDOK=0, CH4SEL=0, CH2SEL=0, GLEN=0, CH5SEL=0, CH6SEL=0, CH3SEL=0

Description

FTM PWM Load

Fields

CH0SEL

Channel 0 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
CH1SEL

Channel 1 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
CH2SEL

Channel 2 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
CH3SEL

Channel 3 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
CH4SEL

Channel 4 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
CH5SEL

Channel 5 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
CH6SEL

Channel 6 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
CH7SEL

Channel 7 Select

0 (0): Channel match is not included as a reload opportunity.

1 (1): Channel match is included as a reload opportunity.
HCSEL

Half Cycle Select

0 (0): Half cycle reload is disabled and it is not considered as a reload opportunity.

1 (1): Half cycle reload is enabled and it is considered as a reload opportunity.
LDOK

Load Enable

0 (0): Loading updated values is disabled.

1 (1): Loading updated values is enabled.
GLEN

Global Load Enable

0 (0): Global Load Ok disabled.

1 (1): Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
GLDOK

Global Load OK

0 (0): No action.

1 (1): LDOK bit is set.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data